Content addressable memory (CAM) devices, sometimes also referred to as “associative memories”, can provide rapid matching functions between an applied data value (e.g., a comparand, compare data, or search key) and stored data values (e.g., entries). Such rapid matching functions are often utilized in routers, network switches, and the like, to process network packets. As but two examples, a CAM can be utilized to search access control lists (ACLs) or forwarding information bases (FIBs). As is well know, an ACL can include a set of rules (data set) that can limit access (e.g., forwarding of packets) to only those packets having fields falling within a particular range. An FIB can include data necessary for forwarding a packet, typically the generation of a “next hop” address in response to a destination address.
A typical CAM device can store a number of data values in a CAM cell array. In a compare (i.e., match) operation, entries can be compared to a compare data value. An entry that matches the compare data value can result in the generation of a match indication.
In a conventional CAM device, search operations can be conducted in response to a system clock, with searches being undertaken every clock cycle. As a result, CAM devices can draw considerable current as match lines in the CAM cell array are continuously charged and discharged each clock cycle.
Current draw in a CAM device can be particularly problematic in the case of a “cold start” operation. A cold start operation can occur when a CAM device switches from an idle state, in which the various CAM array sections of the device are not operational, to an active state, in which CAM array sections perform various functions, such as a search operation, or the like.
Existing conventional approaches can transition from an idle state to a full active state (e.g., search) in a single cycle. This can potentially happen on every other cycle. When a CAM device portion (e.g., a core or block) goes from an idle to an active operation, there can be a very large change in the current requirement for the device. In current and future generation parts, such a current surge may be too large for the on-chip capacitance to support and can happen too quickly for capacitors on circuit boards associated with the CAM device to respond.
Still further, parasitic inductance of a package containing a CAM device, as well as inductance inherent in a CAM device mounting arrangement, can prevent a fast ramp up of the current, preventing an adequate current supply from being provided when needed by the CAM device.
The above deficiencies can result in a power supply voltage “sag” (i.e., level dip) within the CAM device. In addition, the rapid change in current (dl/dt) through parasitic inductive elements can give rise to ground “bounce” (transient jump in a low supply voltage level), which can further disturb CAM operations. These undesirable variations in supply voltages can lead to failures. Such failures are often referred to as “cold start” failures or problems.
To better understand various features and advantages of the disclosed embodiments of the present invention, examples of other CAM device cold start operations will now be described with reference to FIGS. 17A and 17B.
FIG. 17A is a block diagram of one approach for reducing overall transient current in a CAM device. In the arrangement of FIG. 17A, a CAM device 1700 can be divided into two halves 1702-0 and 1702-1, with each half performing a search on opposite edges of a clock signal, and providing results to a synchronizer/priority encoder 1704. In particular, on one type of clock transition (e.g., low-to-high), one side 1702-1 (Panel B) can precharge match lines, while the other side 1702-0 (Panel A) evaluates (i.e., compares a search key to data in CAM entries). On the other clock transition (e.g., high-to-low), the two sides operate in the opposite fashion.
As shown in FIG. 17B, such an arrangement can help to spread out current demand within a cycle. FIG. 17B is a timing diagram showing an average current (I) drawn over time. By providing “intra-clock” activation, power supply transients within one clock cycle can be smoothened.
However, as CAM devices increase in capacity and operating speed, such an approach may not be sufficient to eliminate cold start and related problems. In particular, for higher capacity devices, in the above arrangement, current surges on each clock edge can cause a low power supply level to rise and a high power supply level to sag.
Thus, while the above approach may provide some relief on peak current draw within a single cycle for relatively slower and/or smaller CAM devices, such an arrangement may not address larger CAM devices, or inter cycle current demands or multi-cycle current power supply transients.
Examples of approaches to clocking different portions of CAM device are disclosed in U.S. Pat. No. 6,240,000, titled CONTENT ADDRESSABLE MEMORY WITH REDUCED TRANSIENT CURRENT, issued to Sywyk et al. on May 29, 2001. Another arrangement is disclosed in U.S. patent application Ser. No. 10/746,899, titled STAGGERED COMPARE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORY by Om et al., filed on Dec. 24, 2003, now U.S. Pat. No. 6,958,925. The contents of this application are incorporated by reference herein.
Various approaches for reducing a turn-on current (e.g., cold start current) in a CAM device by sequentially activating sections, and sequentially activating blocks within each section is shown in U.S. patent application Ser. No. 10/940,129, titled REDUCED TURN-ON CURRENT CONTENT ADDRESSABLE MEMORY (CAM) DEVICE AND METHOD by Narum et al., filed on Sep. 14, 2004, now U.S. Pat. No. 7,099,170. This application also describes in greater detail examples of cold start errors. This application is incorporated by reference herein.
In light of the above, it would be desirable to arrive at some way of reducing the rate at which current is drawn (dl/dt) by a CAM device when transitioning from a low (or no) activity state (e.g., start up) to a high activity state. In addition, it would also be desirable to arrive at some way of maintaining a low dl/dt after a device has started up and continues to operate.
It would be desirable if such arrangements did not decrease overall throughput of the CAM device.